Code |
Meaning |
01 |
Processor test part 1. Processor status verification. Tests the following processor-status flags: set/clear carry; zero; sign and overflow (fatal). BIOS sets each flag; verifies they are set and turns each flag off verifying its state. Failure of a flag means a fatal error. Output: infinite loop if failed; continue test if OK. Registers: AX/BP. |
02 |
Determine POST type; whether normal (boot when POST finished) or manufacturing (run 01-05 in loop) which is often set by a jumper on some motherboards. Fails if keyboard interface buffer filled with data. Output: infinite loop if failed; continue test if OK. Registers: AX/BX/BP. |
03 |
Clear 8042 keyboard interface. Send verify TEST_KBRD command (AAh). Output: infinite loop if failed; continue test if OK. Registers: AX/BX/BP. |
04 |
Reset 8042 keyboard controller. Verify AAh return from 03. Infinite loop if test fails. Registers: AX/BX/BP. |
05 |
Get 8042 keyboard controller manufacturing status; read input port via keyboard controller to determine manufacturing or normal mode operation. Reset system if manufacturing; i.e. if 02 found the status to be Manufacturing triggers a reset and 01-05 are repeated continuously. Output: infinite loop if failed; continue test if OK. Registers: AX/BX/BP. |
06 |
Initialise chips on board LSI chips. Disables colour and mono video/parity circuits/DMA (8237) chips; resets maths coprocessor; initialises timer 1 (8255); clears DMA chip and all page registers and the CMOS shutdown byte. |
07 |
Processor Test 2. Reads writes and verifies all CPU registers except SS/SP/BP with data pattern FF and 00. |
08 |
Initialises CMOS timer/RTC and updates timer cycle; normally CMOS (8254) timer; (8237A) DMA; (8259) interrupt and EPROM. |
09 |
EPROM Checksum; test fails if not equal to 0. Also checksums sign-on message. |
0A |
Initialise Video Interface; specifically register 6845 to 80 characters per row and 25 rows per screen and 8/14 scan lines per row for mono/colour; first scan line of cursor 6/11; last scan line of cursor 7/12; reset display offset to 0. |
0B |
Test Timer (8254) Channel 0. See also below. |
0C |
Test Timer (8254) Channel 1. |
0D |
Test Timer (8254) Channel 2. |
0E |
Test CMOS Shutdown Byte using a walking-bit algorithm. |
0F |
Test Extended CMOS. On motherboards supporting extended CMOS configuration such as C & T the BIOS tables of CMOS information configure the chipset which has an extended storage facility enabling you to keep the configuration with the power off. A checksum is used for verification. |
10 |
Test DMA Channel 0. This and the next two tests initialise the DMA chip and test it with an AA/55/FF/00 pattern. Port addresses are used to check the address circuit to DMA page circuit registers. |
11 |
DMA Channel 1 |
12 |
DMA Page Registers |
13 |
Test keyboard controller interface. |
14 |
Test memory refresh toggle circuits. |
15 |
First 64K of system memory which is used by the BIOS; an extensive parity test. |
16 |
Interrupt Vector Table. Sets up and loads interrupt vector tables in memory for the 8259 PIC. |
17 |
Video I/O operations. Initialises the video; EGA and VGA ROMs are used if present. |
18 |
Video memory test for CGA and mono cards (EGA and VGA have their own procedures). |
19 |
Test 8259 mask bits?aChannel 1.Interrupt lines turned alternately off and on. Failure is fatal. |
1A |
8259 Mask Bits?aChannel 2 |
1B |
CMOS battery level; verifies battery status bit set to 1. 0 could indicate bad battery at CMOS. |
1C |
Tests the CMOS checksum data at 2E and 2Fh and extended CMOS checksum if present. |
1D |
Configuration of the system from CMOS values if the checksum is good. |
1E |
System memory size is determined by writing to addresses from 0-640K continuing till there is no response. The size is then compared to the CMOS and a flag set if they do not compare. An error message will then be displayed. |
1F |
Tests memory from the top of 64K to the top of memory found by writing patterns FFAA and 5500 and reading them back byte by byte for verification |
20 |
Stuck 8259 Interrupt Bits. |
21 |
Stuck NMI bits (parity or I/O channel check). |
22 |
8259 function. |
23 |
Verifies protected mode; 8086 virtual and page mode. |
24 |
As for 1E but for extended memory from 1-16Mb on 286/386SX systems and 64 Mb on 386s and above. The value found is compared to the CMOS settings. |
25 |
Tests extended memory found above using virtual 8086 paging mode and writing an FFFF/AA55/0000 pattern. |
26 |
Protected Mode Exceptions; tests other aspects of protected mode operations. |
27 |
Tests cache control (386/486) or Shadow RAM. Systems with CGA and MDA indicate that video shadow RAM is enabled even though there is no BIOS ROM to shadow. |
28 |
Set up cache controller or 8242 keyboard controller. Optional Intel 8242/8248 keyboard controller detection and support. |
29 |
Reserved. |
2A |
Initialise keyboard and controller. |
2B |
Initialise floppy drive(s) and controller. |
2C |
Detect and initialise serial ports. |
2D |
Detect and initialise parallel ports. |
2E |
Initialise hard drive and controller. |
2F |
Detect and initialise maths coprocessor. |
30 |
Reserved. |
31 |
Detect and initialise option ROMs. Initialises any between C800-EFFF. |
3B |
Initialise secondary cache with OPTi chipset (486 only). |
CC |
NMI Handler Shutdown. Detects untrapped NMIs during boot. |
EE |
Unexpected Processor Exception. |
FF |
Boot Attempt; if POST is complete and all components are initialised with no errors. |