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Award ??v3.Ox
??????Uses IBM beep patterns. Version 3.xx sends codes 1-24 to port 80
and 300 and the system hangs up. Afterwards, codes are sent to the POST
port and screen without hanging up.

Code

Meaning

01

CPU test 1: verify CPU status bits

02

Powerup check?aWait for chips to come up; initialize motherboard and chipset (if present) with defaults. Read 8042 status and fail if its input buffer contains data but output buffer does not.

03

Clear 8042 Keyboard interface?asend self-test command AA, fail if status not 2 output buffer full.

04

Reset 8042 Keyboard controller?afail if no data input (status not equal 1) within a million tries, or if input data is not 55 in response to POST 03.

05

Get 8042 manufacturing status?aread video type and POST type bits from 8042 discrete input port; test for POST type = manufacturing test or normal; fail if no response from 8042.

06

Initialize on-board chips?adisable color & mono video, parity, and 8237 DMA; reset 80x87 math chip, initialize 8255 timer 1, clear DMA chip and page registers and CMOS RAM shutdown byte: initialize motherboard chipset if present.

07

CPU test 2: read/write/verify registers except SS, SP, BP with FF and 00 data

08

Initialize CMOS RAM/RTC chip?aupdate timer cycle normally; disable PIE, AIE, UIE and square wave. Set BCD date and 24-hour mode.

09

Checksum 32K of BIOS ROM; fail if not 0

0A

Initialize video interface?aread video type from 8042 discrete input port. Fail if can't read it. Initialize 6845 controller register at either color or mono adapter port to 80 columns, 25 rows, 8/14 scan lines per row, cursor lines at 6/11 (first) & 7/12 (last), offset to 0.

0B

Test 8254 timer channel 0- this test is skipped; already initialized for mode 3.

0C

Test 8254 timer channel 1?athis test is skipped; already initialized for mode 0.

0D

Test 8254 timer channel 2?awrite/read/verify FF, then 00 to timer registers; initialize with 500h for normal operation.

0E

Test CMOS RAM shutdown byte (3.03: CMOS date and timer?athis test is skipped and its functions performed

0F

Test extended CMOS RAM if present (3.03: test CMOS shutdown byte?awrite/read/verify a walk-to-left I pattern at CMOS RAM address 8F)

10

Test 8237 DMA controller ch 0?awrite/read/verify pattern AA, 55, FF and 00.

11

Test 8237 DMA controller ch 1?awrite/read/verify pattern AA, 55, FF and 00.

12

Test 8237 DMA controller page registers?awrite/read/verify pattern AA, 55, FF and 00: use port addresses to check out address circuitry to select page registers. At this point, POST enables user reboot.

13

Test 8741 keyboard controller interface?aread 8042 status, verify buffers are empty, send AA self-test command, verify 55 response, send 8741 write command to 8042, wait for 8042 acknowledgement, send 44 data for 8741 (keyboard enabled, system flag, AT interface), wait for ack, send keyboard disable command, wait for ack. Fail if no ack or improper responses.

14

Test memory refresh toggle circuits?afail if not toggling high and low.

15

Test first 64K of base system memory?adisable parity checking, zero all of memory, 64K at a time, to clear parity errors, enable parity checking, write/read/verify 00, 5A, FF and A5 at each address.

16

Set up interrupt vector tables in low memory.

17

Set up video I/O operations?aread 8042 (motherboard switch or jumper) to find whether color or mono adapter installed; validate by writing a pattern to mono memory B0000 and select mono I/O port if OK or color if not, and initialize it via setting up the hardware byte and issuing INT 10. Then search for special video adapter BIOS ROM at C0000 (EGA/VGA), and call it to initialize if found. Fail if no 8042 response.

18, 1 beep

Test MDA/CGA video memory unless EGA/VGA adapter is found?adisable video, detect mono video RAM at B0000 or color at B8000, write/read/verify test it with pattern A5A5, fill it with normal attribute, enable the video card. No error halt unless enabled by CMOS. Beep once to let user know first phase of testing is complete. From now on, POST will display test and error messages on the screen.

19

Test 8259 PlC mask bits, channel 1?awrite/read/verify 00 to mask register.

1A

Test 8259 PlC mask bits, channel 2?awrite/read/verify 00 to mask register.

1B

Test CMOS RAM battery level?apoll CMOS RTC/RAM chip for battery level status. Display error if level is low, but do not halt.

1C

Test CMOS RAM checksum?acheck CMOS RAM battery level again, calculate checksum of normal and extended CMOS RAM. Halt if low battery or checksum not 0; otherwise reinitialize motherboard chipset if necessary.

1D

Set system memory size parameters from CMOS RAM data, Cannot fail.

1E

Size base memory 64K at a time, and save in CMOS RAM. Cannot fail, but saves diagnostic byte in CMOS RAM if different from size in CMOS.

1F

Test base memory found from 64K to 640K?awrite/read/verify FFAA and 5500 patterns by byte. Display shows failing address and data.

20

Test stuck bits in 8259 PICs

21

Test for stuck NMI bits (parity /I0 check)

22

Test 8259 PlC interrupt functionality?aset up counter timer 0 to count down and issue an interrupt on IRQ8. Fail if interrupt does not occur.

23

Test protected mode, A20 gate. and (386 only) virtual 86 & 8086 page mode.

24

Size extended memory above 1Mb; save size into CMOS RAM. Cannot fail, but saves diagnostic byte in CMOS RAM if different from size in CMOS.

25

Test all base and extended memory found (except the first 64K) up to 16 Mb. Disable parity check but monitor for parity errors. Write/read/verify AA55 then 55AA pattern 64K at a time. On 386 systems use virtual 8086 mode paging system. Displays actual and expected data and failing address.

26

Test protected mode exceptions?acreates the circumstances to cause exceptions and verifies they happen; out-of-bounds instruction, invalid opcode, invalid TSS (JMP, CALL, IRET, INT), segment not present on segment register instruction, generate memory reference fault by writing to a read-only segment.

27

Initialise shadow RAM and move system BIOS and/or video BIOS into it if enabled by CMOS RAM setup. Also (386 only) initialise the cache controller if present in system. This is not implemented in some versions of 3.03

28

Detect and initialise Intel 8242/8248 chip (not implemented in 3.03)

29

Reserved

2A

Initialise keyboard

2B

Detect and initialise floppy drive

2C

Detect and initialise serial ports

2D

Detect and initialise parallel ports

2E

Detect and initialise hard drive

2F

Detect and initialise math coprocessor

30

Reserved

31

Detect and initialise adapter ROMs

BD

Initialize Orvonton cache controller if present

CA

Initialize 386 Micronics cache if present

CC

Shutdown NMI handler

EE

Test for unexpected processor exception

FF

INT 19 boot

BACK

 

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