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486 EISA - 10 Oct 1989
Tandon Type B AT - 1992

Code

Meaning

01

Cold boot started

06

Initialize chipset if any

07

Warm boot entry. About to start 8042 keyboard controller self-test

08

Part of cold boot keyboard initialization passed

09

Keyboard self-test finished. Test ROM BIOS checksum.

0A

Test CMOS RAM battery level

0B

Save CMOS RAM battery condition in CMOS diagnostic/status register

0C

Finished saving CMOS RAM battery condition

0D

Test 8254 PIT. Disable RAM parity, I/O parity, DMA controllers, and speaker; enable timer channel 2.

0E, AA, xx

8245 test failed. xx is the failing channel number.

0F

Initialize 8254 timer channels (0 to mode 3 for 55 ms square wave, 1 to mode 2 as rate generator for refresh) and conduct memory refresh test.

10

Refresh test failed

11

Test base 64K RAM and fill with zeros

12

64K RAM test failed. 3 long beeps and halt.

13

RAM test passed

14

Set up stack, disable mappers for systems that support EMS drivers (for warm boot), initialize battery beep flag parameters for notebook, perform read/write test of CMOS RAM, enable error message if failed.

15

CMOS RAM read/write test complete

16

Calculating CPU speed; may set to low if CMOS RAM failed

18

Test and initialize both 8259 interrupt controllers

1A

8259 initialization complete

1B

Install interrupt handler and vector for INT 0F to check for unexpected (spurious) interrupts. Halt if spurious interrupt occurs.

1C

Spurious interrupt did not occur (test pass). Test 8254 timer channel 0, IRQ0, and software INT8 tests.

1D

Error. Timer 0 interrupt did not occur when expected. Halt system.

1E

Both 8259 interrupt controllers passed the tests

20

Set up interrupt vectors 02-1F

21

Set up interrupt vectors 70-77

22

Clear interrupt vectors for 41 and 46 (disk parameter pointers).

23

Read 8042 self-test result, DMA page reg ch 2 (port 81).

24

Test for proper 8042 self-test result (55).

25

Error: Keyboard controller self-test failed, display message and halt.

26

Keyboard controller self-test passed

27

Confirm DMA working; prepare DMA channel 2 for floppy data transfer

28

Reinitialize video (cold boot)

29

Reinitialize video with cursor off (warm boot)

2A

Video parameters are initialized

2B

Enable NMI and I/O channel check, disable 8254 timer channel 2 and speaker

2C

Run RAM test to determine size of RAM

2D

RAM sizing complete

2E

Send reset command to keyboard controller to initiate a keyboard scan cycle

2F

Keyboard has been initialized. Initialize the CMOS RTC

30

CMOS RTC has been initialized. Initialize on-board floppy if any

31

Install the hard disk controller

32

Disk controller has been installed; prepare DMA channel 2 for floppy transfers

33

Perform equipment check and initialize numeric data processor (math chip)

34

Install the serial/parallel ports

35

Test CMOS RAM battery level

36

Check for keypress?aEsc=Setup, Spacebar=menu; do speed beeps 2=high, l=low

37

Enable 8254 timer channel 0 for system tick, enable keyboard and slave interrupt controller 8259 #2

38

Timer tick, keyboard and 8259 #2 have been enabled; enable/disable cache per CMOS RAM

39

Enable keyboard interface and interrupts. Go to built-in Setup program as necessary; shadow ROMs as appropriate.

3A

Setup finished, so clear the screen and display Please Wait message

3B

Test the fixed and floppy drives

3C

Scan for and invoke the adapter ROMs in C800-E000

3D

Turn off Gate A20; restore vectors 3bh-3fh with temporary interrupt service routines.

3E

Gate A20 is turned off

3F

Invoke INT19 to boot operating system.

These accompanied by 5 long beeps:

Code

Meaning

BF

486-based, 386SX/20c or 386SX/25c processor module boards are used in a system where the WD76C10 chipset is not revision F or above.

CF

CPU on a 486-based processor module has failed its internal self-test.

DF

386SX/20c or 386SX/25c processor module board failed correctly to initialize its on-board cache (bad cache RAM. illegal configuration, etc., or unknown module ID).

EF

Extended CMOS RAM within the WD76C10 chipset failed its self-test

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