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Type B AT ?§C 1992
Tandon 486 EISA - 10 Oct 1989

Code

Meaning

Power on or system reset: enable 8042, RTC; disable 82C601 chip serial, parallel, floppy, hard drive, NMI; check 8042 status.

AA, 01, xx

Show 80486 BIST (built-in self-test) result: xx=00 if OK, FF if not.

01

Disable cache, enable ROM, high speed on, turn off caches, disable EISA NMIs, set master and slave IRQs to edge-triggered, disable reset chaining. disable 82C601 chip but set it valid.

05

Initialize address decoder, 640K RAM; set BIOS as cacheable, enable extended memory.

06

Clear Shutdown Flag.

07

8042 and keyboard test: wait till 8042 buffer empty, disable 8042 command, read 8042 output buffer, set response OK to DMA page reg channel 2.

08

Send 8042 NOP command, self-test command; get 8042 self-test result, send to DMA page reg channel 2.

AA, 01, xx

Show 8042 self-test result: xx=55 if OK

09

Test BIOS ROM checksum; 3 short beeps and halt if bad

0A

Read CMOS registers 3 times to clear pending CMOS RTC interrupts, and disable RTC interrupts. Check battery.

0B

Bad CMOS RAM battery.

0C

Send command to port 61 to disable parity and speaker, enable timer; disable DMA.

0D

Test 8254 counter timer: set all 3 counters to mode 3 (square wave), start them and read the counts.

0E

A counter timer is bad (at least one is 0 and not counting).

AA, 01, xx

Show the failing counter address (xx = 40, 41, or 42), then beep long-short-long-short and halt.

0F

Enable and check memory refresh (set timer 1 to mode 2 for 15 microsecond refresh, and turn on DMA to perform it); delay 1 millisecond and check bit 4 of port 61 for 0-to-1 toggle.

10

Memory refresh failed (no toggle); beep short-long-short, and halt.

11

Check and clear the first 64K of RAM in real mode: disable NMI, clear parity latches, fill 64K with 5555 and check it, then AAAA and check it, then 0000.

AA, 06, mmnn, oopp, qqrr

First 64K memory test failed. mmnn=location lsb, msb; oopp= value read lsb, msb; qqrr=value expected lsb, msb.

AA, 01, xx

Test port 61 for parity error (bits 7, 6=1) and display error xx=value read from port 61 if parity error occurred.

12

First 64K memory test failed. Clear parity latches, give 3 long beeps, and halt.

13

First 64K memory test passed.

14

Reset the warm boot flag (40:72) and test CMOS RAM. Turn off caches, shadow the BIOS, set speed high, calculate high speed and initialize GP flag, set speed low and turn off cache if CMOS not good or CMOS speed not high, otherwise turn on cache and set speed high.

16

Check Shutdown Flag 123x.

17

Reset was cold boot. Set 40:e9 bit 7 (disk_status).

18

Prepare 8259 interrupt controllers; send FF to mask register and check it.

19

Interrupt controller initialization failed; initialize video, display the error message, and halt.

1A

Test interrupt controller: set all 256 ints to slipped interrupt vector. If warm boot (40:e9 bit 7), skip to POST 1E.

1B

Set int 0F to spurious interrupt vector, check for spurious interrupts.

1C

Set int 08 (timer 0) to timer 0 int vector, enable timer and int, wait for int from timer.

1D

Timer interrupt did not occur. Initialize video, display error message and halt.

1E

Initialize interrupt vectors.

1F

Initialize interrupt vectors 00-6F to temporary interrupt service routine.

20

Set vectors for interrupt 02-1F.

21

Set interrupt vectors for 70-77, clear vectors 60-67 and 78-FF.

22

Clear interrupt vectors for 41 and 46 (disk parameter pointers).

23

Read 8042 self-test result from DMA page reg ch 2 (port 81).

24

Test for proper 8042 self-test result (55).

25

8042 self-test failed. Get keyboard controller status, initialize video, display error message, and halt.

26

Initialize 8042 keyboard controller, transfer 128K mem. exp. bit from 8042 to CMOS RAM (IBM compatible, but not used), read state of security switch and initialize RAM variable.

27

Check Shutdown Flag = 123x. No= cold boot.

28

If cold boot or CMOS RAM is bad, install video ROM and establish video, initialize equipment flags according to primary video adapter and CMOS RAM content, initialize POST status, initialize video.

29

If not cold boot and CMOS RAM is OK, install Video ROM and establish video for mono/CGA, initialize equipment flags according to primary video adapter and CMOS RAM contents, initialize video warm boot, initialize video.

2A

Check for bad CMOS RAM and queue the message if so; command port 61 to clear parity latches, disable the speaker and disable timer channel 2; enable NMI.

2B

Check Shutdown Flag = 123x. if warm boot, use memory sizes from CMOS RAM.

2C

If cold boot, turn caches off, test memory for appropriate size, and restore cache status.

2D

Turn off "POST Fail" CMOS RAM bit and display any queued error messages; initialize keyboard RAM (40:17-30) + (40:E0-E7).

2E

Initialize 8042 keyboard controller and test keyboard.

2F

Initialize time of day in the real time clock chip.

30

Test for and install floppy controller.

31

Enable C&T 82C601 chip IDE interface, test for and install hard drive.

32

Test 8259 DMA registers with 55 then AA, and initialize them to 0 (ports D2 and D4).

33

Test for and initialize math coprocessor chip

34

Test for and initialize parallel and serial ports, on and off board.

35

Initialize RAM variables for bad CMOS time, date, checksum, and battery condition.

36

Wait for user to press Esc, space. Check the keyboard lock, clear the keyboard lock override, beep to indicate speed, display any queued messages. Esc=setup, space=boot menu.

37

Enable system clock tick (IRQ0), keyboard (IRQ1), and slave interrupt controller (IRQ2)

38

Initialize RAM variables for Ctrl-Alt-Esc, Ctrl-Alt-Ins

39

Enter setup if user pressed Ctrl-Alt-Esc. If EISA, revert to ISA if tab key pressed.

3A

Clear screen and update equipment flags according to CMOS RAM contents (may have changed during setup). Shadow any ROMs per setup. Enable/disable cache per CMOS RAM.

3B

Initialize floppy and fixed disk drives.

3C

Set POST Fail bit in CMOS RAM, then scan for and invoke adapter option ROMs.

3D

Clear the Shutdown Flag to 0, turn off gate A20 to enable memory wrap in real mode.

3E

Set vectors for interrupts 3B-3F, clear Post Fail bit in CMOS RAM, home the cursor, display any error messages, clear MSW of 32-bit registers (ISC Unix).

3F

Invoke INT 19 to boot operating system.

BACK

 

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