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Award Test Sequence - up to v4.2
Test Sequence v3.0 - v4.2
?? ???? The general procedures below are valid for greater than XT v3.0 and AT v3.02-4.2. The sequence may vary slightly between versions.

Procedure

Meaning

CPU

BIOS sets verifies and resets the error flags in the CPU (i.e. carry; sign; zero; stack overflow). Failure here is normally due to the CPU or system clock.

POST Determination

BIOS determines whether motherboard is set for normal operation or a continuous loop of POST (for testing). If the POST test is cycled 1-5 times over and over either the jumper for this function is set to burn-in or the circuitry involved has failed.

Keyboard Controller

BIOS tests the internal operations of the keyboard controller chip (8042). Failure here is normally due to the keyboard chip.

Burn In Status

1-5 will repeat if the motherboard is set to burn in (you will see the reset light on all the time). If you haven't set the board for burn-in mode, there is a short in the circuitry.

Initialise Chipset

BIOS clears all DMA registers and CMOS status bytes 0E & 0F. BIOS then initialises 8254 (timer). Failure of this test is probably due to the timer chip.

CPU

A bit-pattern is used to verify the functioning of the CPU registers. Failure here is normally down to the CPU or clock chip.

RTC

BIOS verifies that that the real time clock is updating CMOS at normal intervals. Failure is normally the CMOS/RTC or the battery.

ROM BIOS Checksum

BIOS performs a checksum of itself against a predetermined value that will equal 00. Failure is down to the ROM BIOS.

Initialise Video

BIOS tests and initialises the video controller. Failure is normally the video controller (6845) or an improper setting of the motherboard or CMOS.

PIT

BIOS tests the functionality of channels 0 1 2 in sequence. Failure is normally the PIT chip (8254/53).

CMOS Status

Walking-bit pattern tests CMOS shutdown status byte 0F. Failure normally in CMOS.

Extended CMOS

BIOS checks for any extended information of the chipset and stores it in the extended RAM area. Failure is normally due to invalid information and can be corrected by setting CMOS defaults. Further failure indicates either the chipset or the CMOS RAM.

DMA

Channels 0 and 1 are tested together with the page registers of the DMA controller chip(s)?a8237. Failure is normally due to the DMA chips.

Keyboard

The 8042 keyboard controller is tested for functionality and for proper interfacing functions. Failure is normally due to the 8042 chip.

Refresh

Memory refresh is tested; the standard refresh period is 120-140 ns. Failure is normally the PIT chip in ATs or the DMA chip in XTs.

Memory

The first 64K of memory is tested with walking-bit patterns. Failure is normally due to the first bank of RAM or a data line.

Interrupt Vectors

The BIOS interrupt vector table is loaded to the first bank of RAM. Failure here is not likely since memory in this area has been tested. If a failure does occur suspect the BIOS or the PIC.

Video ROM

Video ROM is initialised which performs an internal diagnostic before returning control to the System BIOS. Failure is normally the video adapter or the BIOS.

Video Memory

This is tested with a bit-pattern. This is bypassed if there is a ROM on the video adapter. Failure is normally down to the memory on the adapter.

PIC

The functionality of the interrupt controller chip(s) is tested (8259). Failure is normally down to the 8259 chips but may be the clock.

CMOS Battery

BIOS verifies that CMOS byte 0D is set which indicates the CMOS battery power. Suspect the battery first and the CMOS second.

CMOS Checksum

A checksum is performed on the CMOS. Failure is either incorrect setup or CMOS chip or battery. If the test is passed the information is used to configure the system.

Determine System Memory

Memory up to 640K is addressed in 64K blocks. Failure is normally due to an address line or DMA chip. If all of the memory is not found there is a bad RAM chip or address line in the 64K block above the amount found.

Memory Test

Tests are performed on any memory found and there will normally be a message with the hex address of any failing bit displayed at the end of boot.

PIC

Further testing is done on the 8259 chips.

CPU protected mode

Processor is placed into protected mode and back into real mode; the 8042 is used for this. In case of failure suspect the 8042; CPU; CMOS; or BIOS in that order.

Determine Extended Memory

Memory above 1 Mb is addressed in 64K blocks. The entire block will be inactive if there is a bad RAM chip on a block.

Test Extended Memory

Extended memory is tested with a series of patterns. Failure is normally down to a RAM chip, and the hex address of the failed bit should be displayed.

Unexpected Exceptions

BIOS checks for unexpected exceptions in protected mode. Failure is likely to be a TSR or intermittent RAM failure.

Shadow/Cache

Shadow RAM and cache is activated; failure may be due to the cache controller or chips. Check the CMOS first for invalid information.

8242 Detection

BIOS checks for an Intel 8242 keyboard controller and initialises it if found. Failure may be due to an improper jumper setting or the 8242.

Initialise Keyboard

Failure could be the keyboard or the controller.

Initialise Floppy

All those set in the CMOS. Failure could be incorrect CMOS setup or floppy controller or the drive.

Detect Serial Ports

BIOS searches for and initialises up to four serial ports at 3F8/2F8/3E8 and 2E8. Detection failure is normally due to an incorrect jumper setting somewhere or an adapter failure.

Detect Parallel Ports

BIOS searches for and initialises up to four parallel ports at 378/3BC and 278. Detection failure is normally due to an incorrect jumper setting somewhere or an adapter failure.

Initialise Hard Drive

BIOS initialises any hard drive set in CMOS. Failure could be due to invalid CMOS setup, hard drive or controller.

Detect NPU Coprocessor

Initialisation of any NPU Coprocessor found. Failure is due to either an invalid CMOS setup or the NPU is failing.

Initialise Adapter ROM

Any adapter ROMs between C800 and EFFF are initialised. The ROM will do an internal test before giving back control to the System ROM. Failure is normally due to the adapter ROM or the attached hardware.

Initialise External Cache

Any cache external to the 486 is enabled. Failure would indicate invalid CMOS setup, cache controller or chips.

NMI Unexpected Exceptions

A final check for unexpected exceptions before giving control to the Int 19 boot loader. Failure is normally due to a memory parity error or an adapter.

Boot Errors

Failure when the BIOS attempts to boot off the default drive set in CMOS is normally due to an invalid CMOS drive setup or as given by an error message. If the system hangs there is an error in the Master Boot Record or the Volume Boot Record.

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